From: Steven Kao Date: Wed, 6 Sep 2017 05:32:21 +0000 (+0800) Subject: Tegra: memctrl_v2: allow CPU accesses to TZRAM X-Git-Url: http://git.openwrt.org/%22https:/collectd.org//%22/%22https:/collectd.org/%22?a=commitdiff_plain;h=d6306d14bd4fe50aac29dd422a4c5a5c29fb1166;p=project%2Fbcm63xx%2Fatf.git Tegra: memctrl_v2: allow CPU accesses to TZRAM This patch enables CPU access configuration register to allow accesses to the TZRAM aperture on chips after Tegra186. Change-Id: I0898582f8bd6fd35360ecf8ca5cee21fe35f7aab Signed-off-by: Steven Kao --- diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index bd601e4b..e1203144 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -199,12 +199,21 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) * Reset the access configuration registers to restrict access * to the TZRAM aperture */ - for (index = MC_TZRAM_CLIENT_ACCESS_CFG0; + for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0; index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); index += 4U) { tegra_mc_write_32(index, 0); } + /* + * Enable CPU access configuration registers to access the TZRAM aperture + */ + if (!tegra_chipid_is_t186()) { + val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0); + val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW; + tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val); + } + /* * Set the TZRAM base. TZRAM base must be 4k aligned, at least. */ @@ -232,6 +241,9 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG); val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT; val |= MC_GSC_LOCK_CFG_SETTINGS_BIT; + if (!tegra_chipid_is_t186()) { + val |= MC_GSC_ENABLE_CPU_SECURE_BIT; + } tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val); /* diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index 6a0912e5..8dee5070 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -135,6 +135,7 @@ #define MC_GSC_BASE_LO_MASK U(0xFFFFF) #define MC_GSC_BASE_HI_SHIFT U(0) #define MC_GSC_BASE_HI_MASK U(3) +#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) /* TZDRAM carveout configuration registers */ #define MC_SECURITY_CFG0_0 U(0x70) @@ -165,7 +166,10 @@ #define MC_TZRAM_BASE_LO U(0x2194) #define MC_TZRAM_BASE_HI U(0x2198) #define MC_TZRAM_SIZE U(0x219C) -#define MC_TZRAM_CLIENT_ACCESS_CFG0 U(0x21A0) +#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) +#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) +#define TZRAM_ALLOW_MPCORER (U(1) << 7) +#define TZRAM_ALLOW_MPCOREW (U(1) << 25) /******************************************************************************* * Tegra UART Controller constants